R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 59

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Addressing Mode Instruction Format
Register indirect
with displacement
Register indirect
with displacement
Indexed register
indirect
GBR indirect with
displacement
@(disp:4,Rn)
@(disp:12,Rn)
@(R0,Rn)
@(disp:8,GBR)
Effective Address Calculation
The effective address is the sum of Rn and
a 4-bit displacement (disp). The value of disp is
zero-extended, and remains unchanged for
a byte operation, is doubled for a word
operation, and is quadrupled for a longword
operation.
The effective address is the sum of Rn and
a 12-bit displacement (disp).
The value of disp is zero-extended.
The effective address is the sum of Rn and R0.
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged
for a byte operation, is doubled for a word
operation, and is quadrupled for a longword
operation.
(zero-extended)
(zero-extended)
(zero-extended)
1/2/4
Rn
R0
disp
1/2/4
GBR
disp
disp
Rn
Rn
×
×
+
+
+
+
Rev. 2.00 Sep. 07, 2007 Page 31 of 1164
Rn + disp × 1/2/4
+ disp × 1/2/4
Rn + disp
Rn + R0
GBR
REJ09B0321-0200
Equation
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
Rn + R0
Byte:
GBR + disp
Word:
GBR + disp × 2
Longword: GBR
+ disp × 4
Section 2 CPU