R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 500

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Figure 12.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the
TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3
bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input
capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for
the TGRA_1 and TGRA_2 input capture conditions.
Rev. 2.00 Sep. 07, 2007 Page 472 of 1164
REJ09B0321-0200
Cascaded Operation Example (c)
TGRA_1
TGRA_2
TCNT_1
TIOC1A
TIOC2A
H'FFFF
H'C256
H'9192
H'6128
H'2064
H'0000
TCNT_2 value
Figure 12.23 Cascaded Operation Example (c)
H'0512
H'0512
H'6128
H'0513
H'2064
H'0513
H'C256
H'0514
H'0514
H'9192
Time

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