R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 645

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.8.3
If a TCNT input clock pulse is generated during the T
priority and the counter is not incremented as shown in figure 13.13.
13.8.4
If a compare match event occurs during the T
priority and the compare match signal is inhibited as shown in figure 13.14.
Conflict between TCNT Write and Increment
Conflict between TCOR Write and Compare Match
Figure 13.14 Conflict between TCOR Write and Compare Match
Pφ
Address
Internal write signal
TCNT
TCOR
Compare match signal
Pφ
Address
Internal write signal
TCNT input clock
TCNT
Figure 13.13 Conflict between TCNT Write and Increment
TCNT write cycle by CPU
TCOR write cycle by CPU
T
1
T
N
2
1
TCNT address
N
N
state of a TCOR write cycle, the TCOR write takes
TCOR address
Counter write data
TCOR write data
2
state of a TCNT write cycle, the write takes
T
2
T
Rev. 2.00 Sep. 07, 2007 Page 617 of 1164
2
N + 1
Section 13 8-Bit Timers (TMR)
M
M
Inhibited
REJ09B0321-0200