R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 715

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Bit
0
*
Bit Name
DR
Only 0 can be written to clear the flag after 1 is read.
Initial
Value
0
R/W
R/(W)* Receive Data Ready
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Indicates that the quantity of data in the receive FIFO
data register (SCFRDR) is less than the specified
receive trigger number, and that the next data has not
yet been received after the elapse of 15 ETU from the
last stop bit in asynchronous mode. In clocked
synchronous mode, this bit is not set to 1.
0: Receiving is in progress, or no receive data
[Clearing conditions]
•
•
•
1: Next receive data has not been received
[Setting condition]
•
Note:1. This is equivalent to 1.5 frames with the 8-bit,
remains in SCFRDR after receiving ended normally
DR is cleared to 0 when the chip undergoes a
power-on reset
DR is cleared to 0 when all receive data are read
after 1 is read from DR and then 0 is written
DR is cleared to 0 when all receive data in
SCFRDR are read after the DMAC is activated by
the receive FIFO data full interrupt (RXI)
DR is set to 1 when SCFRDR contains less data
than the specified receive trigger number, and the
next data has not yet been received after the
elapse of 15 ETU from the last stop bit. *
1-stop-bit format. (ETU: elementary time unit)
Rev. 2.00 Sep. 07, 2007 Page 687 of 1164
REJ09B0321-0200
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