R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 857

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 11: Reserved. The written value should always be '0' and the returned value is '0'.
Bits 10 to 8 — Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the
segment TSEG2 ( = PHSEG2) to compensate for edges on the CAN Bus with a negative phase
error. A value from 2 to 8 time quanta can be set as shown below.
Bits 7 and 6: Reserved. The written value should always be '0' and the returned value is '0'.
Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the
synchronisation jump width.
Bits 3 to 1: Reserved. The written value should always be '0' and the returned value is '0'.
Bit 10:
TSG2[2]
0
0
0
0
1
1
1
1
Bit 5:
SJW[1]
0
0
1
1
Bit 9:
TSG2[1]
0
0
1
1
0
0
1
1
Bit 4:
SJW[0]
0
1
0
1
Bit 8:
TSG2[0] Description
0
1
0
1
0
1
0
1
Setting prohibited (Initial value)
PHSEG2 = 2 time quanta (conditionally prohibited) See the table
below for TSG1 and TSG2 setting.
PHSEG2 = 3 time quanta
PHSEG2 = 4 time quanta
PHSEG2 = 5 time quanta
PHSEG2 = 6 time quanta
PHSEG2 = 7 time quanta
PHSEG2 = 8 time quanta
Description
Synchronisation Jump width = 1 time quantum (Initial value)
Synchronisation Jump width = 2 time quanta
Synchronisation Jump width = 3 time quanta
Synchronisation Jump width = 4 time quanta
Section 19 Controller Area Network (RCAN-ET)
Rev. 2.00 Sep. 07, 2007 Page 829 of 1164
REJ09B0321-0200