R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 223

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 8.8
[Legend]
x:
Note: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte
Cache
Instruction
cache
Operand
cache
Don't care
write access
*
CPU Cycle
Instruction
fetch
Prefetch/
read
Write
Neither LRU renewed. LRU is renewed in all other cases.
Cache Operations
Hit/
miss
Hit
Miss
Hit
Miss
Hit
Miss
Write-back mode/
write through mode


Either mode is available x
Write-through mode
Write-back mode
Write-through mode
Write-back mode
Write-through mode
Write-back mode
U Bit



0
1

x

0
1
External Memory
Accession
(through internal bus)
Not generated
Cache renewal cycle is
generated.
Not generated
Cache renewal cycle is
generated.
Cache renewal cycle is
generated
Cache renewal cycle is
generated. Succeedingly
write-back cycle in write-
back buffer is generated
Write cycle CPU issues is
generated.
Write cycle CPU issues is
generated.
Cache renewal cycle is
generated.
Cache renewal cycle is
generated. Succeedingly
write-back cycle in write-
back buffer is generated
Not generated
Rev. 2.00 Sep. 07, 2007 Page 195 of 1164
Cache Contents
Not renewed
Renewed to new values by
cache renewal cycle
Not renewed
Renewed to new values by
cache renewal cycle
Renewed to new values by
cache renewal cycle
Renewed to new values by
cache renewal cycle
Renewed to new values by
write cycle the CPU issues
Renewed to new values by
write cycle the CPU issues
Not renewed*
Renewed to new values by
cache renewal cycle.
Subsequently renewed
again to new values in
write cycle CPU issues.
Renewed to new values by
cache renewal cycle.
Subsequently renewed
again to new values in
write cycle CPU issues.
REJ09B0321-0200
Section 8 Cache