R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 324

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
(2)
The CPU is notified of a bus error through the OR condition of the timeout bits (PTO/ETO) and
illegal address access bits (PER/EER/OER/SHER) in the bus monitor status register 1
(SYCBESTS1) and bus monitor status register 2 (SYCBESTS2). The CPU is notified of a bus
error interrupt according to the setting of the bus error control register (SYCBESW).
When the bus monitor status register 1 (SYCBESTS1) and bus monitor status register 2
(SYCBESTS2) are cleared by the CPU, the bus error interrupt signal is also negated.
(3)
When a bus error is detected, the bus access is terminated. For details, see section 10.2.4,
Combinations of Masters and Bus Errors.
For the detailed operations when each type of error is detected, see section 10.2.2, Illegal Address
Access Detection Function and section 10.2.3, Bus Timeout Detection Function.
10.2.2
The illegal address access detection function detects attempted accesses to illegal addresses.
(1)
Illegal address access errors occur when the following illegal addresses are accessed.
• External spaces for which the operation enable bit (EXENB) in the control register of the BSC
• Other address areas that are not mapped to any slave bus
• Address areas that are mapped to the slave buses but do not correspond to slave devices
Tables 10.3 and 10.4 show the address areas to which slave devices are not mapped within the
spaces for peripheral buses (1) and (2).
Table 10.3 Address Areas without Slave Devices in the Space for Peripheral Bus (1)
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REJ09B0321-0200
is not set to "operation enabled"
Error Notification to the CPU
Termination of Bus Access
Conditions of Illegal Address Access Error Generation
Illegal Address Access Detection Function
FF401000 to FF41FFFF
FF423000 to FF45FFFF
FF464000 to FF5FFFFF