R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 472

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.22 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Rev. 2.00 Sep. 07, 2007 Page 444 of 1164
REJ09B0321-0200
Bit
7
6
Bit Name
—
BDC
Figure 12.3 PWM Output Level Setting Procedure in Buffer Operation
Set bit TOCS
Set TOCR2
Set TOLBR
Initial value:
Initial
value
1
0
R/W:
Bit:
[1]
[2]
[3]
—
R/W
R
R/W
R
7
1
BDC
R/W
6
0
[1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting.
[2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer
[3] The TOLBR initial setting must be the same value as specified in
Description
Reserved
This bit is always read as 1. The write value should
always be 1.
Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P
to specify the PWM output levels.
bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
R/W
N
5
0
R/W
P
4
0
R/W
FB
3
0
R/W
WF
2
0
R/W
VF
1
0
R/W
UF
0
0