R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 82

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.4.7
Table 2.16 System Control Instructions
Rev. 2.00 Sep. 07, 2007 Page 54 of 1164
REJ09B0321-0200
Instruction
CLRT
CLRMAC
LDBANK
LDC
LDC
LDC
LDC
LDC.L
LDC.L
LDC.L
LDS
LDS
LDS
LDS.L
LDS.L
LDS.L
NOP
RESBANK
RTE
SETT
SLEEP
STBANK
Rm,SR
@Rm+,SR
Rm,MACH
@Rm+,MACH
@Rm+,MACL
@Rm+,PR
@Rm,R0
Rm,TBR
Rm,GBR
Rm,VBR
@Rm+,GBR
@Rm+,VBR
Rm,MACL
Rm,PR
R0,@Rn
System Control Instructions
Instruction Code
0000000000001000
0000000000101000
0100mmmm11100101
0100mmmm00001110
0100mmmm01001010
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000001011011
0000000000101011
0000000000011000
0000000000011011
0100nnnn11100001
Operation
0 → T
0 → MACH,MACL
(Specified register bank entry)
→ R0
Rm → SR
Rm → TBR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm 1
(Rm) → MACL, Rm + 4 → Rm 1
(Rm) → PR, Rm + 4 → Rm
No operation
Bank → R0 to R14, GBR,
MACH, MACL, PR
Delayed branch,
stack area → PC/SR
1 → T
Sleep
R0 →
(specified register bank entry)
Execu-
tion
Cycles
1
1
6
3
1
1
1
5
1
1
1
1
1
1
1
9*
6
1
5
7
T Bit
0


LSB



LSB











1


SH2,
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes