R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 658

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Watchdog Timer (WDT)
14.4.3
1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR,
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the
5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated
6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin,
Rev. 2.00 Sep. 07, 2007 Page 630 of 1164
REJ09B0321-0200
Internal
reset signal*
[Legend]
WT/IT:
TME:
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
WDTOVF
signal
whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it
is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT.
the counter from overflowing.
WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset
the system. The WDTOVF signal is output for 64 × Pφ clock cycles.
simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be
selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for
128 × Pφ clock cycles.
the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.
WTCNT value
H'FF
H'00
Timer mode select bit
Timer enable bit
Using Watchdog Timer Mode
WT/IT = 1
TME = 1
Figure 14.4 Operation in Watchdog Timer Mode
H'00 written
in WTCNT
WDTOVF and internal reset generated
64 × Pφ clock cycles
WOVF = 1
128 × Pφ clock cycles
Overflow
WT/IT = 1
TME = 1
H'00 written
in WTCNT
Time