R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 463

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.17 Timer Read/Write Enable Register (TRWER)
TRWER is an 8-bit readable/writable register that enables or disables access to the registers and
counters which have write-protection capability against accidental modification in channels 3 and
4.
• Registers and counters having write-protection capability against accidental modification
Bit
7 to 1
0
22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3,
TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1,
TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT_4.
Bit Name
—
RWE
Initial value:
Initial
Value
All 0
1
R/W:
Bit:
—
R/W
R
R/W
R
7
0
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Read/Write Enable
Enables or disables access to the registers which have
write-protection capability against accidental
modification.
0: Disables read/write access to the registers
1: Enables read/write access to the registers
[Clearing condition]
•
—
R
5
0
When 0 is written to the RWE bit after reading
RWE = 1
—
R
4
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
—
R
3
0
Rev. 2.00 Sep. 07, 2007 Page 435 of 1164
—
R
2
0
—
R
1
0
RWE
R/W
0
1
REJ09B0321-0200