R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 471

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 12.38 TIOC3B Output Level Select Function
12.3.21 Timer Output Level Buffer Register (TOLBR)
TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies
the PWM output level in complementary PWM mode and reset-synchronized PWM mode.
Figure 12.3 shows an example of the PWM output level setting procedure in buffer operation.
Bit 0
OLS1P
0
1
Bit
7, 6
5
4
3
2
1
0
Bit Name
—
OLS3N
OLS3P
OLS2N
OLS2P
OLS1N
OLS1P
Initial Output
High level
Low level
Initial value:
Initial
value
All 0
0
0
0
0
0
0
R/W:
Bit:
Active Level
Low level
High level
—
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
7
0
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies the buffer value to be transferred to the
OLS3N bit in TOCR2.
Specifies the buffer value to be transferred to the
OLS3P bit in TOCR2.
Specifies the buffer value to be transferred to the
OLS2N bit in TOCR2.
Specifies the buffer value to be transferred to the
OLS2P bit in TOCR2.
Specifies the buffer value to be transferred to the
OLS1N bit in TOCR2.
Specifies the buffer value to be transferred to the
OLS1P bit in TOCR2.
OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
R/W
5
0
Up Count
Low level
High level
R/W
Function
4
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
3
0
Rev. 2.00 Sep. 07, 2007 Page 443 of 1164
R/W
Compare Match Output
2
0
R/W
1
0
R/W
0
0
Down Count
Low level
High level
REJ09B0321-0200