R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 599
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 599 of 1196
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(5)
Figure 12.129 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in complementary PWM mode after re-setting.
1 to 10 are the same as in figure 12.125.
11. Initialize the normal mode waveform generation section with TIOR.
12. Disable operation of the normal mode waveform generation section with TIOR.
13. Disable channel 3 and 4 output with TOER.
14. Select the complementary PWM output level and cyclic output enabling/disabling with
15. Set complementary PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU2 output with the PFC.
18. Operation is restarted by TSTR.
MTU2
module
TIOC3A
TIOC3B
TIOC3D
Port output
PB16
PB17
PB19
TOCR.
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Complementary PWM Mode
output
Power-on
reset
1
(normal)
TMDR
2
High-Z
High-Z
High-Z
TOER
(1)
Figure 12.129 Error Occurrence in Normal Mode,
3
(1 init
0 out)
TIOR
4
Recovery in Complementary PWM Mode
(MTU2)
PFC
5
TSTR
(1)
6
Match
7
occurs
Error
8
(PORT)
PFC
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
9
TSTR
(0)
10
(0 init
0 out)
TIOR
Rev. 2.00 Sep. 07, 2007 Page 571 of 1164
11
(disabled)
TIOR
12
TOER
13
(0)
TOCR
14
(CPWM)
TMDR
15
REJ09B0321-0200
TOER
(16)
(1)
(MTU2)
PFC
(17)
TSTR
(18)
(1)
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