R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 887

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.6.3
(1)
The following sequence is an example to transmit a CAN frame onto the bus. As described in the
previous register section, please note that IRR8 is set when one of the TXACK or ABACK bits is
set, meaning one of the Mailboxes has completed its transmission or transmission abortion and is
now ready to be updated for the next transmission, whereas, the GSR2 means that there is
currently no transmission request made (No TXPR flags set).
(2)
The following diagram explains how RCAN-ET manages to schedule transmission-requested
messages in the correct order based on the CAN identifier. 'Internal arbitration' picks up the
highest priority message amongst transmit-requested messages.
Note: n = 0 to 15 (mailbox number)
Message Transmission Request
Internal Arbitration for Transmission
RCAN-ET is in Normal Mode
Write '1' to the TXPR[n] bit
Update Message Data of
Message Transmission Sequence
at any desired time
'n' Highest Priority?
Transmission Start
Internal Arbitration
(MBC[n] = 0)
Mailbox[n]
Yes
CAN Bus
Arbitration
Figure 19.9 Transmission Request
No
Mailbox[n] is ready
to be updated for
next transmission
Clear TXACK[n]
TXACK[n] set?
IRR8 set?
Yes
Yes
Acknowledge Bit
Section 19 Controller Area Network (RCAN-ET)
Rev. 2.00 Sep. 07, 2007 Page 859 of 1164
No
No
CAN Bus
Monitor for the next interrupt
Monitor for the next interrupt
REJ09B0321-0200