R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 747

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In serial reception, the SCIF operates as described below.
1. The SCIF synchronizes with serial clock input or output and starts the reception.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
Figure 16.15 shows an example of SCIF receive operation.
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If
the check is not passed (overrun error is detected), further reception is prevented.
the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in
SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Serial clock
Serial data
RDF
ORER
Figure 16.14 Sample Flowchart for Receiving Serial Data (2)
Figure 16.15 Example of SCIF Receive Operation
RXI
interrupt
request
Bit 7
LSB
No
Data read from SCFRDR and
RDF flag cleared to 0 by RXI
interrupt handler
Bit 0
Clear ORER flag in SCLSR to 0
One frame
Overrun error handling
Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
ORER = 1?
Bit 7
MSB
End
Yes
Bit 0
RXI
interrupt
request
Rev. 2.00 Sep. 07, 2007 Page 719 of 1164
Bit 1
Bit 6
BRI interrupt request
by overrun error
Bit 7
REJ09B0321-0200