R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 241

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.3
To disable the operation for each channel, forcibly write out data tentatively stored in internal
write buffer. The procedure is as follows:
1. Execute read access to the channel whose operation is to be disabled.
Bit
31 to 22 
21, 20
19 to 17 
16
15 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAMCm Control Register (SDCmCNT) (m = 0, 1)
Bit Name

BSIZE[1:0]
EXENB
—
—
31
15
R
R
0
0
—
—
30
14
R
R
0
0
—
—
29
13
R
R
0
0
Initial
Value
All 0
00
All 0
0
All 0
—
—
28
12
R
R
0
0
—
—
27
11
R
R
0
0
R/W
R
R/W
R
R/W
R
—
—
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
External Bus Width Select
These bits specify the width of the data bus for the
external device of the corresponding channel of CSC.
10: 8-bit bus
00: 16-bit bus
01: 32-bit bus
Reserved
These bits are always read as 0. The write value
should always be 0.
Operation Enable
This bit enables or disables the operation for the
corresponding channel of CSC.
0: Operation disabled
1: Operation enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
—
—
25
R
R
0
9
0
—
24
—
R
R
0
8
0
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 213 of 1164
22
—
—
R
R
0
6
0
Section 9 Bus State Controller (BSC)
R/W
BSIZE[1:0]
21
—
R
0
5
0
R/W
20
—
R
0
4
0
19
—
—
R
R
0
3
0
REJ09B0321-0200
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
EXENB
R/W
16
—
R
0
0
0