R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 651

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3
The WDT has the following registers.
Table 14.2 Register Configuration
Note:
14.3.1
WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock
signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in
watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a
power-on reset caused by the RES pin or in deep standby mode or software standby mode.
Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read
from WTCNT.
Note: The method for writing to WTCNT differs from that for other registers to prevent
Register Name
Watchdog timer counter
Watchdog timer control/status
register
Watchdog reset control/status
register
*
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Register Descriptions
Watchdog Timer Counter (WTCNT)
For the access size, see section 14.3.4, Notes on Register Access.
Initial value:
R/W:
Bit:
R/W
0
7
Abbreviation R/W
WTCNT
WTCSR
WRCSR
R/W
0
6
R/W
0
5
R/W
0
4
R/W
R/W
R/W
R/W
3
0
Rev. 2.00 Sep. 07, 2007 Page 623 of 1164
Initial
Value
H'00
H'18
H'1F
R/W
0
2
R/W
Section 14 Watchdog Timer (WDT)
1
0
R/W
H'FFFE0002
H'FFFE0000
H'FFFE0004
Address
0
0
REJ09B0321-0200
Access
Size
16*
16*
16*