R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 449

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.7
TBTM is an 8-bit readable/writable register that specifies the timing for transferring data from the
buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers,
one each for channels 0, 3, and 4.
Bit
7 to 3
2
1
Bit Name
—
TTSE
TTSB
Timer Buffer Operation Transfer Mode Register (TBTM)
Initial value:
Initial
Value
All 0
0
0
R/W:
Bit:
—
R/W
R
R/W
R/W
R
7
0
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timing Select E
Specifies the timing for transferring data from TGRF_0
to TGRE_0 when they are used together for buffer
operation.
For channels 3 and 4, bit 2 is reserved. It is always read
as 0 and the write value should always be 0.
Do not set this bit to 1 when channel 0 is to be used in
a mode other than PWM mode.
0: When compare match E occurs in channel 0
1: When TCNT_0 is cleared
Timing Select B
Specifies the timing for transferring data from TGRD to
TGRB in each channel when they are used together for
buffer operation.
Do not set this bit to 1 when the channel is to be used
in a mode other than PWM mode.
0: When compare match B occurs in each channel
1: When TCNT is cleared in each channel
—
R
5
0
—
R
4
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
—
R
3
0
TTSE TTSB TTSA
Rev. 2.00 Sep. 07, 2007 Page 421 of 1164
R/W
2
0
R/W
1
0
R/W
0
0
REJ09B0321-0200