R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 96

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 Floating-Point Unit (FPU)
3.3.2
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and
selects the rounding mode.
Rev. 2.00 Sep. 07, 2007 Page 68 of 1164
REJ09B0321-0200
Bit
31 to 23
22
21
20
19
18
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Floating-Point Status/Control Register (FPSCR)
Bit Name
—
QIS
—
SZ
PR
DN
R/W
31
15

R
0
0
R/W
30
14

R
0
0
Cause
R/W
29
13

R
0
0
Initial
Value
All 0
0
0
0
0
1
R/W
28
12

R
0
0
R/W
27
11

R
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
26
10

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Nonnunerical Processing Mode
0: Processes qNaN or ±∞ as such
1: Treats qNaN or ±∞ as the same as sNaN (valid only
Reserved
This bit is always read as 0. The write value should
always be 0.
Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
Precision Mode
0: Floating-point instructions are executed as
1: Floating-point instructions are executed as
FPU)
1: Denormalized number is treated as zero
Denormalization Mode (Always fixed to 1 in SH2A-
Enable
R/W
when the V bit in FPSCR enable is set to 1)
25
pair (64 bits)
single-precision operations
double-precision operations (graphics support
instructions are undefined)

R
0
9
0
R/W
24

R
0
8
0
R/W
23

R
0
7
0
R/W
R/W
QIS
22
6
0
0
R/W
21

R
5
0
0
Flag
R/W
R/W
SZ
20
0
4
0
R/W
R/W
PR
19
0
3
0
R/W
DN
18
R
1
2
0
RM1
R/W
R/W
17
0
1
0
Cause
RM0
R/W
R/W
16
0
0
1