R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 654

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Watchdog Timer (WDT)
14.3.3
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
WRCSR is initialized to H'1F by input of a reset signal from the RES pin or in deep standby
mode, but is not initialized by the internal reset signal generated by overflow of the WDT.
WRCSR is initialized to H'1F in software standby mode.
Note: The method for writing to WRCSR differs from that for other registers to prevent
Rev. 2.00 Sep. 07, 2007 Page 626 of 1164
REJ09B0321-0200
Bit
7
6
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Watchdog Reset Control/Status Register (WRCSR)
Bit Name
WOVF
RSTE
Initial value:
0
Initial
Value
0
R/W:
Bit:
WOVF
R/(W)
0
7
R/W
R/(W)
R/W
RSTE
R/W
0
6
RSTS
R/W
Watchdog Timer Overflow
Reset Enable
Description
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
•
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and
0
5
When 0 is written to WOVF after reading WOVF
—
1
R
4
WTCSR reset within WDT.
—
R
3
1
—
R
2
1
—
R
1
1
—
R
0
1