R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 267

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

1. Ts (Internal Bus Access Start)
2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait)
3. Tend (Wait End Cycle)
This is a bus access request cycle initiated by the internal bus master and with the external bus
as the target. CSn is always high during this cycle. In the next cycle A27 to A0 and the write
data change.
These are the cycles between internal bus access start and the wait end cycle. A duration of
from 0 to 31 clocks may be selected. During this interval the CSn, RD, and WR control signals
are asserted (low level) in accordance with the wait settings. The assert timing can be
controlled using the CS assert wait, RD assert wait, WR assert wait, and write data output wait
bits in CSn control registers 1 and 2. The number of wait cycles can be set to from 0 to 7
clocks, with the count starting from the cycle following internal bus access start (Ts). The
number of clocks selected must be no greater than the number of read/write cycle wait cycles.
This is the final cycle in a series of read cycle wait or write cycle wait cycles. The RD or WR
signal is negated (high level) in the next cycle.
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Ts
Figure 9.3 Basic Bus Timing (Write Operation)
Tw1 Tw2
CS assert wait
WR assert wait
Write data output wait
Write cycle wait
Twn
Tend
Rev. 2.00 Sep. 07, 2007 Page 239 of 1164
Tn1
Write data output delay cycle
cycle during write
Section 9 Bus State Controller (BSC)
CS delay
Tnm
Start enable point
of next bus access
REJ09B0321-0200