R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 245

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.5
CS1WCNTn specifies the number of wait states inserted into the read/write cycle or page
read/page write cycle.
Bit
31 to 29 
28 to 24 CSRWAIT
23 to 21 
20 to 16 CSWWAIT
15 to 11 
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6)
Bit Name
[4:0]
[4:0]
31
—
15
—
R
R
0
0
30
—
14
—
R
R
0
0
29
—
13
—
R
R
0
0
Initial
Value
All 0
11111
All 0
11111
All 0
R/W
28
12
—
R
1
0
R/W
27
11
—
R
1
0
CSRWAIT[4:0]
R/W
R
R/W
R
R/W
R
R/W
R/W
26
10
CSPRWAIT[2:0]
1
1
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Read Cycle Wait Select
These bits specify the number of wait states inserted
into the initial normal read cycle and page read cycle.
00000: 0 wait states
11111: 31 wait states
Reserved
These bits are always read as 0. The write value
should always be 0.
Write Cycle Wait Select
These bits specify the number of wait states inserted
into the initial normal write cycle and page write cycle.
00000: 0 wait states
11111: 31 wait states
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
R/W
25
1
9
1
:
:
R/W
R/W
24
1
8
1
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 217 of 1164
22
—
—
R
R
0
6
0
Section 9 Bus State Controller (BSC)
21
—
—
R
R
0
5
0
R/W
20
—
R
1
4
0
R/W
19
—
R
1
3
0
CSWWAIT[4:0]
REJ09B0321-0200
R/W
R/W
18
CSPWWAIT[2:0]
1
2
1
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1