R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 694

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
• The quantity of data in the transmit and receive FIFO registers and the number of receive
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 16.1 shows a block diagram of the SCIF.
Rev. 2.00 Sep. 07, 2007 Page 666 of 1164
REJ09B0321-0200
TxD
SCK
RxD
receive-error interrupts are requested independently.
power.
errors of the receive data in the receive FIFO register can be ascertained.
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
SCFRDR (16 stage)
SCRSR
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
Parity check
SCFTDR (16 stage)
Figure 16.1 Block Diagram of SCIF
Parity generation
SCTSR
Module data bus
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
Transmission/reception
control
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count register
Line status register
SCSPTR
SCSMR
SCFDR
SCFCR
SCFSR
SCSCR
SCLSR
External clock
Clock
Baud rate
generator
SCIF
SCBRR
P φ
P φ /4
P φ /16
P φ /64
TXI
RXI
ERI
BRI
Peripheral
bus