R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 456

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.13 Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for
channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5.
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers.
TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers.
TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD.
TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the
TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for
operation as a buffer register. TGR buffer register combination is TGRE and TGRF.
TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse
width measurement registers.
Rev. 2.00 Sep. 07, 2007 Page 428 of 1164
REJ09B0321-0200
Initial value:
Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits.
R/W:
Bit:
TGR registers are initialized to H'FFFF.
R/W
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1