R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 746

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Clocked Synchronous Mode)
Figures 16.13 and 16.14 show sample flowcharts for receiving serial data. When switching from
asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that
ORER, PER, and FER are cleared to 0.
Rev. 2.00 Sep. 07, 2007 Page 718 of 1164
REJ09B0321-0200
No
No
Figure 16.13 Sample Flowchart for Receiving Serial Data (1)
Read ORER flag in SCLSR
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Read receive data in
flag in SCFSR to 0
All data received?
Start of reception
End of reception
ORER = 1?
RDF = 1?
No
Yes
Yes
Error handling
[2]
[3]
Yes
[1]
[1] Receive error handling:
[2] SCIF status check and receive data read:
[3] Serial reception continuation procedure:
Read the ORER flag in SCLSR to identify
any error, perform the appropriate error
handling, then clear the ORER flag to 0.
Reception cannot be resumed while the
ORER flag is set to 1.
Read SCFSR and check that RDF = 1,
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
of the RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, read at least
the receive trigger set number of receive
data bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
SCFRDR. However, the RDF bit is
cleared to 0 automatically when an RXI
interrupt activates the DMAC to read the
data in SCFRDR.