R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 631

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
13.3.5
TCCR selects the TCNT internal clock source and controls external reset input.
Bit
7 to 4
3
2
1, 0
Bit Name
TMRIS
ICKS[1:0]
Timer Counter Control Register (TCCR)
00
Initial
Value
All 0
0
0
Initial value:
R/W:
Bit:
R/W
R/W
R/W
R/W
R/W
R/W
0
7
R/W
0
6
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timer Reset Input Select
Selects an external reset input when the CCLR1 and
CCLR0 bits in TCR are B'11.
0: Cleared at rising edge of the external reset
1: Cleared when the external reset is high
Reserved
This bit is always read as 0. The write value should
always be 0
Internal Clock Select 1 and 0
These bits in combination with bits CKS2 to CKS0 in TCR
select the internal clock. See table 13.2.
R/W
0
5
R/W
0
4
TMRIS
R/W
0
3
Rev. 2.00 Sep. 07, 2007 Page 603 of 1164
R/W
0
2
R/W
ICKS[1:0]
1
0
Section 13 8-Bit Timers (TMR)
R/W
0
0
REJ09B0321-0200

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