R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 809

no-image

R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is
Bit
1
0
2. The SSI clock must be kept supplied until the SSI is in the idle state.
Bit Name
SWNO
IDST
ignored.
Initial
Value
1
1*
2
R/W
R
R
Description
System Word Number
This status bit indicates the current word number.
Idle Mode Status Flag
This status flag indicates that the serial bus activity has
stopped.
This bit is cleared if EN = 1 and the serial bus are
currently active.
This bit is automatically set to 1 under the following
conditions.
Note: If the external master stops the serial bus clock
TRMD = 0 (Receive mode)
SWNO indicates which system word the data in
SSIRDR currently represents. This value will
change as the data in SSIRDR is updated from the
shift register, regardless of whether SSIRDR has
been read.
TRMD = 1 (Transmit mode)
SWNO indicates which system word is required to
be written to SSITDR. This value will change as the
data is copied to the shift register, regardless of
whether the data is written to SSITDR.
SSI = Master transmitter (SWSD = 1 and
TRMD = 1)
This bit is set to 1 if the EN bit is cleared and the
data written to SSITDR is completely output from
the serial data input/output pin (SSIDATA), that is,
the output of the system word length is completed.
SSI = Master receiver (SWSD = 1 and TRMD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
SSI = Slave transmitter/receiver (SWSD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
before the current system word is completed,
this bit is not set.
Rev. 2.00 Sep. 07, 2007 Page 781 of 1164
Section 18 Serial Sound Interface (SSI)
REJ09B0321-0200

Related parts for R5S72011