R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 360

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Sep. 07, 2007 Page 332 of 1164
REJ09B0321-0200
Bit
8
7 to 1
Bit Name
ECLR

Initial
Value
0
All 0
R/W
R
R/W
Description
DMA Transfer Enable Clear
This bit specifies whether or not to clear the DMA
transfer enable bit (DEN) to "0" when the DMA transfer
end condition is detected.
When this bit is cleared to "0", the DMA transfer
enable bit (DEN) is not cleared to "0" even when the
DMA transfer end condition is detected.
When this bit is set to "1", the DMA transfer enable bit
(DEN) is cleared to "0" when the DMA transfer end
condition is detected.
Note:
0: Detection of the DMA transfer end condition does
1: Detection of the DMA transfer end condition clears
Reserved
These bits are always read as 0. The write value
should always be 0.
not clear the DMA transfer enable bit to 0
the DMA transfer enable bit to 0
When a value is written to the DMA transfer
enable clear bit for a channel handling single
operand transfer, operation is not guaranteed.