R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 336

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.3.1
DMCSADR is a register used to specify the start address of the transfer source.
The value in this register is transferred to the working source-address register at the start of DMA
transfer.
The default behavior is for the contents of the working source-address register to be returned on
completion of single operand transfer. However, the contents of the working source address
register are not returned in two cases: when the rotate setting (SAMOD = 011) is made for the
source address and when the source-address reload function is enabled. In the latter case, the
contents of the DMA reload source address register (DMRSADRn) are returned to this register on
completion of DMA transfer.
This register must be set before transfer is initiated, regardless of whether the reload function is
enabled or disabled.
Notes: 1. Set this register so that DMA transfer is performed within the correctly aligned address
Rev. 2.00 Sep. 07, 2007 Page 308 of 1164
REJ09B0321-0200
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. Only write to this register when single operand transfer is not in process on the
DMA Current Source Address Register (DMCSADR)
Bit Name
CSA
R/W
R/W
•
•
boundaries for the transfer sizes listed below.
corresponding channel (the corresponding DASTS bit in the DMA arbitration status
register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation
control register (DMSCNT) or DEN in DMA control register B for the channel
(DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when
both conditions are not satisfied.
31
15
—
—
When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
R/W
R/W
30
14
—
—
R/W
R/W
29
13
—
—
Initial
Value
Undefined R/W
R/W
R/W
28
12
—
—
R/W
R/W
27
11
—
—
R/W
R/W
R/W
26
10
—
—
Description
Holds source address bits A31 to A0
R/W
R/W
25
—
—
9
R/W
R/W
24
—
—
8
CSA
CSA
R/W
R/W
23
—
—
7
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
R/W
R/W
18
—
—
2
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0