R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 222

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Cache
(2)
In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced follows table 8.4. When the U bit of the entry to be replaced is 1,
the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written
to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way
becomes the latest. After the cache completes its update cycle, the write-back buffer writes the
entry back to the memory. The write-back unit is 16 bytes.
In write-through mode, no write to cache occurs in a write miss; the write is only to the external
memory.
8.3.5
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the cache completes to fetch the new entry, the write-back buffer writes
the entry back to external memory. During the write-back cycles, the cache can be accessed. The
write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 8.3
shows the configuration of the write-back buffer.
Operations in sections 8.3.2 to 8.3.5 are compiled in table 8.8
Rev. 2.00 Sep. 07, 2007 Page 194 of 1164
REJ09B0321-0200
Write Miss
A (31 to 4):
Longword 0 to 3: One line of cache data to be written to external memory
A (31 to 4)
Write-Back Buffer (Only for Operand Cache)
Physical address written to external memory (upper three bits are 0)
Figure 8.3 Write-Back Buffer Configuration
Longword 0
Longword 1
Longword 2
Longword 3