R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 262

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
9.4.16
SDSTR consists of the status flags that indicate the status of operation during self-refresh,
initialization sequences, power-down mode, deep-power-down mode, and mode register setting.
Rev. 2.00 Sep. 07, 2007 Page 234 of 1164
REJ09B0321-0200
Bit
31 to 5
4
3
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAM Status Register (SDSTR)
Bit Name

DSRFST
DINIST
31
15
—
—
R
R
0
0
—
—
30
14
R
R
0
0
—
—
Initial
Value
All 0
0
0
29
13
R
R
0
0
—
—
28
12
R
R
0
0
—
—
27
11
R
R
0
0
R/W
R
R
R
—
—
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Self-Refresh Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from self-refresh operation is in progress for
channel SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
Initialization Status
When set to 1, this bit indicates that an initialization
sequence is in progress for channel SDRAM0 or
SDRAM1. This bit has the same function as the
DINIST bit in SDIR1.
0: Initialization sequence not in progress
1: Initialization sequence in progress
—
—
25
R
R
0
9
0
24
—
—
R
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
DSRF
20
—
ST
R
R
0
4
0
DINI
19
—
ST
R
R
0
3
0
DPWD
18
—
ST
R
R
0
2
0
DDPD
17
—
ST
R
R
0
1
0
DMRS
16
—
ST
R
R
0
0
0