R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 738

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Asynchronous Mode)
Figures 16.6 and 16.7 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Rev. 2.00 Sep. 07, 2007 Page 710 of 1164
REJ09B0321-0200
No
No
ER, DR, BRK or ORER = 1?
Read ER, DR, BRK flags in
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Read receive data in
SCFSR and ORER
flag in SCFSR to 0
All data received?
Start of reception
End of reception
flag in SCLSR
Figure 16.6 Sample Flowchart for Receiving Serial Data
RDF = 1?
No
Yes
Yes
Error handling
[1]
[2]
[3]
Yes
[1] Receive error handling and break detection:
[2] SCIF status check and receive data read:
[3] Serial reception continuation procedure:
ORER flag in SCLSR, to identify any error, perform the
appropriate error handling, then clear the DR, ER,
BRK, and ORER flags to 0. In the case of a framing
error, a break can also be detected by reading the
value of the RxD pin.
receive data in SCFRDR, read 1 from the RDF flag,
and then clear the RDF flag to 0. The transition of the
RDF flag from 0 to 1 can also be identified by an RXI
interrupt.
trigger set number of receive data bytes from
SCFRDR, read 1 from the RDF flag, then clear the
RDF flag to 0. The number of receive data bytes in
SCFRDR can be ascertained by reading from
SCRFDR.
Read the DR, ER, and BRK flags in SCFSR, and the
Read SCFSR and check that RDF = 1, then read the
To continue serial reception, read at least the receive