R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 217

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Bit
31 to 17
16
15 to 10
9
8
7 to 2
1
0
*
Bit Name

LE

W3LOAD*
W3LOCK

W2LOAD*
W2LOCK
The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Initial
Value
All 0
0
All 0
0
0
All 0
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Lock Enable
Enables or disables the cache locking function.
0: Non-cache locking mode
1: Cache locking mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Way 3 Load
Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
Reserved
These bits are always read as 0. The write value should
always be 0.
Way 2 Load
Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK =1 in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the cache miss data is loaded into the
way to which LRU points.
Rev. 2.00 Sep. 07, 2007 Page 189 of 1164
REJ09B0321-0200
Section 8 Cache