R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 320

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
Rev. 2.00 Sep. 07, 2007 Page 292 of 1164
REJ09B0321-0200
Bit
25, 24
23 to 14 
13
12 to 10 
9, 8
7, 6
5
Bit Name
EMST[1:0]
OER
OMST[1:0]

SHER
Initial
Value
00
All 0
0
All 0
00
All 0
0
R/W
R
R
R
R
R/W
R
R
Description
Bus Master
These bits indicate the bus master that accessed the
external bus when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Illegal Address Access
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
0: Illegal address access not made
1: Illegal address access made
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Master
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (2) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made