R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 339

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.3.4
DMRSADR is used to set an address for reloading to the DMA current source address register
(DMCSADRn).
To enable reloading, set the DMA source address reload function enable bit (SRLOD) in DMA
control register A (DMCNTAn) for the channel to "1". In this case, set both the DMA current
source address register (DMCSADRn) and DMA reload source address register (DMRSADRn).
Note: Set this register so that DMA transfer is performed within the correctly aligned address
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
boundaries for the transfer sizes listed below.
•
•
2. Set this register so that DMA transfer is performed within the correctly aligned address
3. Only write to this register when single operand transfer is not in process on the
DMA Reload Source Address Register (DMRSADR)
Bit Name
RSA
R/W
R/W
When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
•
•
boundaries for the transfer sizes listed below.
corresponding channel (the corresponding DASTS bit in the DMA arbitration status
register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation
control register (DMSCNT) or DEN in DMA control register B for the channel
(DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when
both conditions are not satisfied.
31
15
—
—
When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
R/W
R/W
30
14
—
—
R/W
R/W
29
13
—
—
Initial
Value
Undefined R/W
R/W
R/W
28
—
12
—
R/W
R/W
27
—
11
—
R/W
R/W
R/W
26
—
10
—
Description
Holds source address bits A31 to A0 for reloading
R/W
R/W
25
—
—
9
R/W
R/W
24
—
—
8
Section 11 Direct Memory Access Controller (DMAC)
RSA
RSA
R/W
R/W
23
—
—
7
Rev. 2.00 Sep. 07, 2007 Page 311 of 1164
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
REJ09B0321-0200
R/W
R/W
18
—
—
2
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0