R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 196

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
7.3.5
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus
cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as
the break conditions. BBR is initialized to H'0000 by a power-on reset and in deep standby, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Rev. 2.00 Sep. 07, 2007 Page 168 of 1164
REJ09B0321-0200
Bit
15, 14
13
12
11 to 8
Initial value:
R/W:
Bit:
Break Bus Cycle Register (BBR)
Bit Name

UBID
DBE
CP[3:0]
15

R
0
14

R
0
UBID DBE
R/W
13
0
Initial
Value
All 0
0
0
0000
R/W
12
0
R/W
11
0
R/W
R
R/W
R/W
R/W
R/W
10
0
CP[3:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Interrupt Disable
Disables or enables user break interrupt requests
when a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
1: Data bus condition is included in break conditions
I-Bus Bus Select
Select the bus master when the bus cycle of the break
condition is the I bus cycle. However, when the C bus
cycle is selected, this bit is invalidated (only the CPU
cycle).
xxx1: CPU cycle is included in break conditions
xx1x: Reserved. Setting prohibited
x1xx: Reserved. Setting prohibited
1xxx: Reserved. Setting prohibited
R/W
0
9
conditions
R/W
0
8
R/W
0
7
CD[1:0]
R/W
0
6
R/W
0
5
ID[1:0]
R/W
0
4
R/W
0
3
RW[1:0]
R/W
2
0
R/W
1
0
SZ[1:0]
R/W
0
0