R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 479

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.29 Timer Buffer Transfer Set Register (TBTER)
TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer
registers* used in complementary PWM mode to the temporary registers and specifies whether to
link the transfer with interrupt skipping operation. The MTU2 has one TBTER.
Note:
Bit
7 to 2
1, 0
*
Bit Name
—
BTE[1:0]
Applicable buffer registers:
TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR
Initial value:
Initial
Value
All 0
00
R/W:
Bit:
—
R/W
R
R/W
R
7
0
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
These bits enable or disable transfer from the buffer
registers* used in complementary PWM mode to the
temporary registers and specify whether to link the
transfer with interrupt skipping operation.
For details, see table 12.42.
—
R
5
0
—
R
4
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
—
R
3
0
Rev. 2.00 Sep. 07, 2007 Page 451 of 1164
—
R
2
0
R/W
BTE[1:0]
1
0
R/W
0
0
REJ09B0321-0200