R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 41

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Classification
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to IRQ0
PINT7 to PINT0 I
A27 to A0
D31 to D0
CS6 to CS0
RD
WAIT
WR0
WR1
WR2
WR3
I/O
I
I
O
I/O
O
O
I
O
O
O
O
Name
Non-maskable
Chip select 6 to 0 Chip-select signals for external
Read
Wait
Byte select
Byte select
Byte select
Byte select
interrupt
Interrupt requests
7 to 0
Interrupt requests
7 to 0
Address bus
Data bus
Rev. 2.00 Sep. 07, 2007 Page 13 of 1164
Function
Non-maskable interrupt request pin.
Fix it high when not in use.
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Maskable interrupt request pins.
Only level-input detection can be
selected.
Addresses are output on these pins.
Bidirectional data bus
memory or devices
Indicates that data is read from an
external device.
Input pin for inserting a wait cycle
into the bus cycles during access to
the external space
Indicates a write access to bits 7 to 0
of data of external memory or
device. (For an access in units of 8,
16, or 32 bits)
Indicates a write access to bits 15 to
8 of data of external memory or
device. (For an access in units of 16
or 32 bits)
Indicates a write access to bits 23 to
16 of data of external memory or
device. (For an access in units of 32
bits)
Indicates a write access to bits 31 to
24 of data of external memory or
device. (For an access in units of 32
bits)
Section 1 Overview
REJ09B0321-0200