R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 329
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 329 of 1196
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The DMA controller (hereafter DMAC) is a module that handles high-speed data transfer without
CPU intervention in response to requests from software, on-chip peripheral I/O modules, or
external pins (external modules). The DMAC itself does not distinguish between requests from
on-chip peripheral I/O or external pins (external modules). The DMA supports data transfer
between memory units, memory and I/O modules, and I/O modules.
11.1
• Channel number: Up to eight channels (with four channels capable of external requests)
• Transfer requests: Requests from 37 sources including software trigger, on-chip peripheral I/O,
• Maximum transfer bytes: 64 Mbytes
• Address space: 4 Gbytes
• Transfer data sizes:
• Transfer mode:
• Maximum transfer speed:
• Transfer conditions:
• Channel priority:
and external pins (external modules)
Single data transfer: 8, 16, 32, 64, and 128 bits
Single operand transfer: 1, 2, 4, 8, 16, 32, 64, and 128 data
Non-stop transfer: Up to the byte count "0"
Cycle-stealing transfer (dual-address transfer)
Pipelined transfer (dual-address transfer)
Cycle-stealing transfer: Minimum of three clock cycles per unit data transfer
Pipelined transfer: Minimum of one clock cycle per unit data transfer
Unit operand transfer: a single sequence of single operand data transfer in response to a
Sequential operand transfer: single operand transfers are repeated until the byte count
Non-stop transfer: data is continuously transferred until the byte count reaches "0" in
Channel 0 > channel 1 > → > channel 6 > channel 7 (this priority order is fixed)
Section 11 Direct Memory Access Controller (DMAC)
DMA request
reaches "0"
response to a single DMA request
Features
Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Sep. 07, 2007 Page 301 of 1164
REJ09B0321-0200
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