R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 927

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3.1
DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be
performed. Whenever analog output is enabled, the values in DADR are converted and output to
the analog output pins.
DADR is initialized to H'00 by a power-on reset in deep standby mode or module standby mode.
21.3.2
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a power-on reset in deep standby mode or module standby mode.
Bit
7
6
Bit Name
DAOE1
DAOE0
D/A Data Registers 0 and 1 (DADR0 and DADR1)
D/A Control Register (DACR)
Initial
Value
0
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
R/W
R/W
R/W
DAOE1 DAOE0 DAE
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
Description
D/A Output Enable 1
Controls D/A conversion and analog output for channel 1.
0: Analog output of channel 1 (DA1) is disabled
1: D/A conversion of channel 1 is enabled. Analog output
D/A Output Enable 0
Controls D/A conversion and analog output for channel 0.
0: Analog output of channel 0 (DA0) is disabled
1: D/A conversion of channel 0 is enabled. Analog output
of channel 1 (DA1) is enabled.
of channel 0 (DA0) is enabled.
R/W
R/W
5
0
5
0
R/W
—
—
4
0
4
1
R/W
—
—
3
0
3
1
Rev. 2.00 Sep. 07, 2007 Page 899 of 1164
R/W
—
—
2
0
2
1
R/W
—
—
1
0
1
1
Section 21 D/A Converter (DAC)
R/W
—
—
0
0
0
1
REJ09B0321-0200