R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 674

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Realtime Clock (RTC)
15.3.9
RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the
RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From
among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and
alarm register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
The assignable range is from 00 through 59 + ENB bits (practically in BCD), otherwise operation
errors occur.
The ENB bit in RSECAR is initialized to 0 by a power-on reset or in deep standby mode. The
other bits are not initialized by a power-on reset or manual reset, or in deep standby and software
standby modes.
Rev. 2.00 Sep. 07, 2007 Page 646 of 1164
REJ09B0321-0200
Bit
7
6 to 4
3 to 0
Bit Name
ENB
10 seconds Undefined R/W
1 second
Second Alarm Register (RSECAR)
Initial value:
Initial
Value
0
Undefined R/W
R/W:
Bit:
ENB
R/W
7
0
R/W
R/W
R/W
—
6
10 seconds
Description
When this bit is set to 1, a comparison with the
Ten's position of seconds setting value
One's position of seconds setting value
RSECCNT value is performed.
R/W
—
5
R/W
—
4
R/W
—
3
R/W
1 second
—
2
R/W
—
1
R/W
—
0