R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 874

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET)
19.5.3
The TXACK0 is a 16-bit read/conditionally-write registers. This register is used to signal to the
CPU that a mailbox transmission has been successfully made. When a transmission has succeeded
the RCAN-ET sets the corresponding bit in the TXACK register. The CPU may clear a TXACK
bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect.
• TXACK0
Note: * Only when writing a '1' to clear.
Bit 15 to 1 — Notifies that the requested transmission of the corresponding Mailbox has been
finished successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has
no effect and always read back as a '0'.
Rev. 2.00 Sep. 07, 2007 Page 846 of 1164
REJ09B0321-0200
Bit[15:1]:TXACK0
0
1
Initial value:
R/W:
Bit:
Transmit Acknowledge Register 0 (TXACK0)
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
0
14
0
Description
[Clearing Condition] Writing '1' (Initial value)
Corresponding Mailbox has successfully transmitted message (Data or
Remote Frame)
[Setting Condition] Completion of message transmission for corresponding
mailbox
13
0
12
0
11
0
10
0
9
0
TXACK0[15:1]
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
—
0
0
0