R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 637

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.4
13.4.1
Figure 13.2 shows an example of the 8-bit timer being used to generate a pulse output with a
desired duty cycle. The control bits are set as follows:
1. In TCR, clear bit CCLR1 to 0 and set bit CCLR0 to 1 so that TCNT is cleared at a TCORA
2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA
With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a
pulse width determined by TCORB. No software intervention is required. The output level of the
8-bit timer holds 0 until the first compare match occurs after a reset.
compare match.
compare match and to 0 at a TCORB compare match.
Operation
Pulse Output
TCORA
TCORB
TMO
H'FF
H'00
Figure 13.2 Example of Pulse Output
TCNT
Counter clear
Rev. 2.00 Sep. 07, 2007 Page 609 of 1164
Section 13 8-Bit Timers (TMR)
REJ09B0321-0200