R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 788

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
Rev. 2.00 Sep. 07, 2007 Page 760 of 1164
REJ09B0321-0200
2
C Bus Interface 3 (IIC3)
No
No
No
Clear TRS in ICCR1 to 0
Figure 17.20 Sample Flowchart for Slave Transmit Mode
Dummy-read ICDRR
Slave transmit mode
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear TDRE in ICSR
Clear AAS in ICSR
Write transmit data
Write transmit data
TEND = 1 ?
TDRE = 1 ?
Last byte?
in ICDRT
in ICDRT
End
Yes
Yes
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1] Clear the AAS flag.
[2] Set transmit data for ICDRT (except for the last byte).
[3] Wait for ICDRT empty.
[4] Set the last byte of transmit data.
[5] Wait for the last byte to be transmitted.
[6] Clear the TEND flag.
[7] Set slave receive mode.
[8] Dummy-read ICDRR to release the SCL.
[9] Clear the TDRE flag.