R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 801

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
15
14
13
12
Bit Name
SCKD
SWSD
SCKP
SWSP
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Serial Bit Clock Direction
0: Serial bit clock is input, slave mode.
1: Serial bit clock is output, master mode.
Note: SSI0 and SSI1 permit only the following setting:
Serial WS Direction
0: Serial word select is input, slave mode.
1: Serial word select is output, master mode.
Note: SSI0 and SSI1 permit only the following setting:
Serial Bit Clock Polarity
0: SSIWS and SSIDATA change at the SSISCK falling
1: SSIWS and SSIDATA change at the SSISCK rising
Serial WS Polarity
0: SSIWS is low for 1st channel, high for 2nd channel.
1: SSIWS is high for 1st channel, low for 2nd channel.
SSIDATA input sampling timing at
the time of reception (TRMD = 0)
SSIDATA output change timing at
the time of transmission (TRMD = 1)
SSIWS input sampling timing at
the time of slave mode (SWSD = 0)
SSIWS output change timing at
the time of master mode (SWSD = 1)
edge (sampled at the SCK rising edge).
edge (sampled at the SCK falling edge).
(SCKD, SWSD) = (0,0) and (1,1). Other settings
are prohibited.
(SCKD, SWSD) = (0,0) and (1,1). Other settings
are prohibited.
Rev. 2.00 Sep. 07, 2007 Page 773 of 1164
Section 18 Serial Sound Interface (SSI)
SCKP = 0
SSISCK rising
edge
SSISCK falling
edge
SSISCK rising
edge
SSISCK falling
edge
REJ09B0321-0200
SCKP = 1
SSISCK falling
edge
SSISCK rising
edge
SSISCK falling
edge
SSISCK rising
edge