R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 829

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

When an underflow or overflow error condition has matched, the CHNO [1:0] bit and the SWNO
bit can be used to recover the SSI module to a known status. When an underflow or overflow
occurs, the host can read the channel number and system word number to determine what point the
serial audio stream has reached. In the transmitter case, the host can skip forward through the data
it wants to transmit until it finds the sample data that matches what the SSI module is expecting to
transmit next, and so resynchronize with the audio data stream. In the receiver case the host CPU
can store null data to make the number of receive data items consistent until it is ready to store the
sample data that the SSI module is indicating will be received next, and so resynchronize with the
audio data stream.
18.4.6
The following procedures can be used for implementation.
(1)
1. Set SSICR.DMEN = 0 (disabling a DMA request) to stop the DMA transfer.
2. Wait for SSISR.DIRQ = 1 (transmit mode: the transmit buffer is empty) using a polling,
3. With SSICR.EN = 0 (disabling an SSI module operation), stop the transfer.
4. Before attempting another transfer, make sure that SSISR.IDST = 1 is reached.
5. Set SSICR.EN = 1 (enabling an SSI module operation).
6. Wait for SSISR.DIRQ = 1, using a polling, interrupt, or the like.
7. Setting SSICR.DMEN = 1 (enabling a DMA request) will restart the DMA transfer.
(2)
1. Set SSICR.DMEN = 0 (disabling a DMA request) to stop the DMA transfer.
2. Wait for SSISR.DIRQ = 1 (transmit mode: the transmit buffer is empty), using a polling,
3. With SSICR.EN = 0 (disabling an SSI module operation), stop the transfer.
4. Stop the DMAC with DMSCNT of the DMAC.
5. Before attempting another transfer, make sure that SSISR.IDST = 1 is reached.
6. Set SSICR.EN = 1 (enabling an SSI module operation).
7. Set the DMAC registers and start the transfer.
8. Setting SSICR.DMEN = 1 (enabling a DMA request) will restart the DMA transfer.
interrupt, or the like.
interrupt, or the like.
Procedure for the Repeated Transfer and Stop without having to Reconfigure the
DMAC
Procedure for Reconfiguring the DMAC after an SSI stop
Temporary Stop and Restart Procedures in Transmit Mode
Rev. 2.00 Sep. 07, 2007 Page 801 of 1164
Section 18 Serial Sound Interface (SSI)
REJ09B0321-0200