R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 281

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(6)
SDRAMC is provided with a sequencer for issuing the commands for SDRAM initialization. The
initialization sequence should always be initiated a single time only following a reset (all
channels) and following recovery from deep-power-down mode (individual channels). In such
cases operation cannot be guaranteed if the initialization sequence is not performed, or if it is
performed more than once.
The SDRAM initialization sequence issues the precharge-all-banks command followed by n (n = 1
to 15) auto-refresh commands, in that order. Make timing settings for the initialization sequencer
to SDRAM initialization register 0 (SDIR0). Initialization sequences are initiated using SDRAM
initialization register 1 (SDIR1).
Note that an initialization sequence for all channels is initiated using the DINIRQ bit.
Figure 9.10 shows a timing example for the initialization sequence. Setting DARFC to specify two
or more times causes multiple initialization auto-refresh cycles to be performed.
Initialization Sequencer
(DPC Bit Set Value: 001, DARFI Bit Set Value: 0001, DARFC Bit Set Value: 001)
CKIO
SDRAM command
Figure 9.10 Initialization Sequence Timing Example
DSL: Deselect command
RFA: Auto-refresh command
PRA: Precharge-all-banks command
Initialization precharge cycle
PRA
DSL
DPC
DSL
DSL
Initialization auto-refresh cycle
RFA
Rev. 2.00 Sep. 07, 2007 Page 253 of 1164
DSL
Section 9 Bus State Controller (BSC)
DARFI
DSL
DINST bit value
changes to 0
DSL
REJ09B0321-0200