R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 126

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Handling
Notes: 1. Some registers are excluded. For details, see section 28.3, Register States in Each
5.2.3
(1)
When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this
LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at
power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc when
the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip
peripheral module registers are initialized. See appendix A, Pin States, for the status of individual
pins during the power-on reset state.
In the power-on reset state, power-on reset exception handling starts when the RES pin is first
driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
Be certain to always perform power-on reset processing when turning the system power on.
Rev. 2.00 Sep. 07, 2007 Page 98 of 1164
REJ09B0321-0200
Type
Manual
reset
exception handling vector table.
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized to 0. The BN bit in IBNR of the INTC is also initialized to 0. FPSCR is initialized to
H'00040001.
program begins executing.
Power-On Reset by Means of RES Pin
2. The BN bit in IBNR of the INTC is initialized.
Power-On Reset
RES
High
High
Operating Mode.
Conditions for Transition to Reset State
H-UDI Command MRES
Command other
than H-UDI reset
assert is set
Command other
than H-UDI reset
assert is set
Low
High
WDT
Overflow
—
Manual
reset
CPU
Initialized
Initialized
On-Chip
Peripheral
Modules, I/O Port
Not initialized *
Not initialized *
Internal States
2
2
WRCSR of
WDT, FRQCR
of CPG
Not initialized
Not initialized