R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 709

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
7
Bit Name
ER
Initial
Value
0
R/W
R/(W)* Receive Error
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Indicates the occurrence of a framing error, or of a
parity error when receiving data that includes parity. *
0: Receiving is in progress or has ended normally
[Clearing conditions]
•
•
1: A framing error or parity error has occurred.
[Setting conditions]
•
•
Notes: 1. Clearing the RE bit to 0 in SCSCR does
ER is cleared to 0 a power-on reset
ER is cleared to 0 when the chip is when 0 is
written after 1 is read from ER
ER is set to 1 when the stop bit is 0 after checking
whether or not the last stop bit of the received
data is 1 at the end of one data receive
operation*
ER is set to 1 when the total number of 1s in the
receive data plus parity bit does not match the
even/odd parity specified by the O/E bit in SCSMR
2. In two stop bits mode, only the first stop
not affect the ER bit, which retains its
previous value. Even if a receive error
occurs, the receive data is transferred to
SCFRDR and the receive operation is
continued. Whether or not the data read
from SCFRDR includes a receive error
can be detected by the FER and PER bits
in SCFSR.
bit is checked; the second stop bit is not
checked.
2
Rev. 2.00 Sep. 07, 2007 Page 681 of 1164
REJ09B0321-0200
1