R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 60

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 32 of 1164
REJ09B0321-0200
Addressing Mode Instruction Format
Indexed GBR
indirect
TBR duplicate
indirect with
displacement
PC indirect with
displacement
PC relative
@(R0,GBR)
@@ (disp:8,TBR) The effective address is the sum of TBR value
@(disp:8,PC)
disp:8
Effective Address Calculation
The effective address is the sum of GBR value
and R0.
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
The effective address is the sum of PC value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
The effective address is the sum of PC value
and the value that is obtained by doubling the
sign-extended 8-bit displacement (disp).
(zero-extended)
(zero-extended)
(sign-extended)
H'FFFFFFFC
GBR
R0
disp
disp
disp
TBR
PC
2/4
PC
4
2
×
&
×
×
+
+
(for longword)
+
+
PC & H'FFFFFFFC
GBR + R0
PC + disp × 2
+ disp × 4)
PC + disp × 2
+ disp × 4
+ disp × 4
(TBR
TBR
or
Equation
GBR + R0
Contents of
address (TBR +
disp × 4)
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC +
disp × 4
PC + disp × 2